Graduate Computer Architecture
Onur MutluOnur Mutlu and the SAFARI Research Group's graduate Computer Architecture lectures at ETH Zürich examining DRAM latency reduction, memory controllers, memory contention & QoS scheduling, on-chip interconnects, and network-on-chip router microarchitecture.
Syllabus
6Main Memory Latency Reduction & Low-Latency DRAM Architectures
An in-depth examination of memory latency and the intricate design of memory controllers, crucial components in high-performance computer architecture.
Memory Controller Microarchitecture, Row Policies & Request Scheduling
Explore the fundamental design and operational principles of memory controllers, a critical component in the performance and reliability of modern computer architectures.
Frontier Research in Processing-in-Memory & Hardware Security
Lecture 11 from ETH Zürich's Computer Architecture course features current research talks from the SAFARI Research Group, highlighting advancements in the field.
Multi-Core Memory Contention, Fairness & QoS-Aware Scheduling
An in-depth examination of memory controllers, their impact on performance and service quality, and the complexities of memory contention in advanced computer systems.
On-Chip Interconnect Topologies, Buffering & Flow Control
Delve into the foundational principles and advanced challenges of interconnect design within high-performance computer architectures, presented by ETH Zürich.
Network-on-Chip (NoC) Router Microarchitecture & Adaptive Routing
An advanced lecture from ETH Zürich exploring the intricate design and operational principles of on-chip networks and router architectures in modern computer systems.