Silicon Gates to High-Performance Analytical Engines
Digital architecture, compiler vectorization, C++ zero-overhead design, and columnar OLAP
Connects ETH Zürich hardware architecture (Mutlu), MIT 6.172 software performance engineering (Leiserson), C++ value semantics (Stroustrup), and CMU vectorized OLAP engines (Pavlo).
Curriculum sequence
7
Digital Design and Computer Architecture - L1: Intro: Fundamentals, Transistors, Gates (Spring 2025)
Grounds computation in CMOS transistors, logic gates, and hardware abstraction layers.
Digital Design and Computer Architecture - L2: Combinational Logic (Spring 2025)
Builds combinational logic blocks and boolean trade-offs that dictate instruction latency.
1. Introduction and Matrix Multiplication
Demonstrates 50,000x matrix-multiply speedups via cache locality, SIMD, and multicore tiling.
2. Bentley Rules for Optimizing Work
Systematizes Jon Bentley's work-reduction rules across loops, data layout, and branches.
The Essence of C++: Zero-Overhead Abstraction
Shows how compile-time types and RAII map high-level abstractions directly onto machine memory.
S2024 #01 - Modern OLAP Database Systems (CMU Advanced Database Systems)
Applies hardware-conscious vectorization to modern analytical database execution engines.
S2024 #02 - Data Formats & Encoding Part 1 (CMU Advanced Database Systems)
Dissects Parquet/Arrow columnar encodings that feed SIMD pipelines at memory bandwidth.