Digital Design and Computer Architecture

This introductory lecture from ETH Zürich's Digital Design and Computer Architecture course systematically builds foundational understanding, beginning with the electrical principles of transistors and their aggregation into fundamental logic gates.

This lecture systematically introduces the principles of combinational logic, detailing Boolean algebra, truth tables, and fundamental logic gates (AND, OR, NOT, XOR) essential for constructing digital circuits. It also covers methods for circuit minimization.

This lecture covers the foundational principles of sequential logic, examining the design and operation of state-holding elements such as latches and flip-flops, and their integration into synchronous and asynchronous digital circuits and finite state machines.

This lecture delves into advanced sequential logic concepts, practical laboratory exercises for digital design, and the application of Verilog for hardware description and FPGA implementation.

This lecture delves into advanced sequential logic design, covering state machine implementation, practical laboratory considerations, and an introduction to hardware description using the Verilog HDL for digital circuits.

This lecture segment from Professor Onur Mutlu's ETH Zürich course delves into advanced aspects of Hardware Description Languages, specifically Verilog for digital circuit description. It examines critical considerations for timing analysis and formal verification methods within complex digital system design.

This lecture, part of ETH Zürich's Computer Architecture course, elaborates on synchronous digital circuit timing analysis, including setup and hold times, clock skew, and formal verification methodologies for robust hardware design.

This lecture introduces the foundational Von Neumann architecture, detailing its core components and operational principles. It then transitions to instruction set architectures, examining their design choices and impact on system performance.

Continuing the discussion on instruction set architectures, this session delves into advanced topics such as addressing modes, instruction formats, and their implications for compiler design and system efficiency. Various ISA paradigms are compared and contrasted.

This lecture explores the critical interface between instruction set architecture (ISA) and microarchitecture. It explains how ISA directives translate into microarchitectural operations and fundamental design principles are introduced.

This segment provides an introduction to assembly language programming, focusing on direct interaction with processor instructions. Students learn fundamental assembly constructs and their mapping to higher-level language operations.

This lecture continues the deep dive into microarchitecture design, examining advanced concepts and design methodologies. It covers the intricate relationships between different microarchitectural components and their performance impact.

This lecture introduces the principles of multi-cycle processor design, contrasting it with single-cycle implementations. It then transitions to pipelined processor design, illustrating how parallelism enhances instruction throughput.

This lecture delves into advanced concepts of pipelined processor design, building upon foundational principles. It examines techniques for managing data hazards, control hazards, and structural hazards to optimize instruction throughput and execution efficiency within CPU architectures.

This lecture details the mechanisms for achieving precise exceptions in computer architecture, examining how hardware state is restored accurately following an exception event in pipelined and out-of-order processors.

This lecture introduces out-of-order execution, a crucial technique for enhancing processor performance by executing instructions as soon as their operands are ready. It covers concepts like reservation stations and reorder buffers.

This lecture covers dataflow principles and their application in superscalar architectures, enabling parallel instruction dispatch. It also thoroughly examines branch prediction techniques to mitigate control hazards and improve pipeline efficiency.

This specific session addresses the complex mechanisms of load and store instruction handling within out-of-order execution pipelines. It discusses memory disambiguation and ordering rules to ensure correct program behavior.

This lecture delves into advanced branch prediction algorithms and their empirical performance. It explores techniques such as two-level adaptive predictors, correlating predictors, and neural branch predictors.

This lecture introduces Very Long Instruction Word (VLIW) architectures, discussing their compiler-managed parallelism. It then examines systolic arrays, a specialized architecture for high-throughput, regular computations.

This lecture introduces Single Instruction, Multiple Data (SIMD) architectures, detailing their principles for data-level parallelism and examining various SIMD implementations in modern processors and accelerators.