RISC-V Processor Design Course - Lecture 1: Introduction and Development Environment Setup
Marco Spaziani BrunellaMarco Spaziani Brunella
PhD, Industry Professional; Former Educator in RISC-V Computer Architecture
15:40·2025·undergraduate level·Standalone Lecture
This inaugural lecture introduces the RISC-V processor design course, outlining the foundational concepts and guiding students through the initial setup of the development environment. It establishes the pedagogical approach for subsequent modules.
Complete SystemVerilog Bootcamp here: https://www.udemy.com/course/systemverilog-for-rtl-design/?referralCode=87BDF3B6F79F40DBD9E2
Slides, lecture notes, codebase 👉🏻 https://github.com/siliscale/Tiny-Vedas
Referenced inHacker News
Comments
Add a comment...Sign in
