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ETH Zürich: Digital Design and Computer Architecture →0/21
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Digital Design and Computer Architecture - L1: Intro: Fundamentals, Transistors, Gates (Spring 2025)

1:44:24
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Digital Design and Computer Architecture - L2: Combinational Logic (Spring 2025)

1:48:06
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Digital Design and Computer Architecture - L3: Sequential Logic (Spring 2025)

1:47:35
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Digital Design and Computer Architecture - L4: Sequential Logic II, Labs, Verilog (Spring 2025)

1:33:54
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Digital Design and Comp. Arch. - Recorded Lecture 4: Sequential Logic II, Labs, Verilog

1:23:51
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Digital Design and Computer Architecture - L5: HDL, Verilog II, Timing & Verification

1:48:14
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Digital Design and Computer Architecture - L6: Timing & Verification II (Spring 2025)

1:49:42
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Lecture 7: Von Neumann Model & Instruction Set Architectures (Spring 2025)

1:50:32
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Lecture 8: Instruction Set Architectures II (Spring 2025)

1:47:52
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Lecture 9: ISA and Microarchitecture (Spring 2025)

1:47:54
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Lecture 9c: Assembly Programming (Spring 2025)

39:59
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Lecture 10: Microarchitecture Fundamentals and Design II (Spring 2025)

1:47:35
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Lecture 11: Multi-Cycle and Pipelined Processor Design (Spring 2025)

1:48:05
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Lecture 12: Pipelined Processor Design II (Spring 2025)

1:48:10
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Lecture 13: Precise Exceptions (Spring 2025)

1:32:02
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Lecture 14: Out-of-Order Execution (Spring 2025)

1:36:14
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Lecture 15: Dataflow, Superscalar Execution & Branch Prediction (Spring 2025)

1:51:29
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Lecture 15c: Load-Store Handling in Out-of-Order Execution (Spring 2025)

24:03
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Lecture 16: Advanced Branch Prediction (Spring 2025)

1:50:47
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Lecture 17: VLIW and Systolic Array Architectures (Spring 2025)

1:49:39
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Lecture 18: SIMD Architectures (Spring 2025)

1:51:16

Lecture 11: Multi-Cycle and Pipelined Processor Design (Spring 2025)

Onur MutluETH Zürich

Professor

1:48:05·2025·undergraduate level

This lecture introduces the principles of multi-cycle processor design, contrasting it with single-cycle implementations. It then transitions to pipelined processor design, illustrating how parallelism enhances instruction throughput.

Systems & CSEngineeringComputer ArchitecturePipeliningMulti-Cycle ProcessorProcessor Design

Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (https://safari.ethz.ch/ddca/spring2025/)

Lecture 11: Multi-Cycle and Pipelined Processor Design

Lecturer: Prof. Onur Mutlu

Previous · Lecture 12

Lecture 10: Microarchitecture Fundamentals and Design II (Spring 2025)

Next · Lecture 14

Lecture 12: Pipelined Processor Design II (Spring 2025)

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