Mechanical Sympathy: Designing Software for Modern CPU Caches
Demonstrates how cache lines, false sharing, store buffers, branch prediction, and lock-free ring buffers govern orders-of-magnitude latency differences on modern hardware.
Peer-curated academic archive from GOTO Conferences, comprising 1 recorded lecture in Computer Systems & Software.
Self-contained research seminars, public lectures, and invited colloquia.
Demonstrates how cache lines, false sharing, store buffers, branch prediction, and lock-free ring buffers govern orders-of-magnitude latency differences on modern hardware.
Professors, researchers, and invited lecturers recorded at GOTO Conferences.
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