Mechanical Sympathy: Designing Software for Modern CPU Caches
Demonstrates how cache lines, false sharing, store buffers, branch prediction, and lock-free ring buffers govern orders-of-magnitude latency differences on modern hardware.
Co-Creator of LMAX Disruptor & Aeron
Self-contained public lectures, keynote addresses, and research seminars.
Demonstrates how cache lines, false sharing, store buffers, branch prediction, and lock-free ring buffers govern orders-of-magnitude latency differences on modern hardware.