Digital Design and Computer Architecture - L1: Intro: Fundamentals, Transistors, Gates
1:44:24Digital Design and Computer Architecture - L2: Combinational Logic
1:48:06Digital Design and Computer Architecture - L3: Sequential Logic
1:47:35Digital Design and Computer Architecture - L4: Sequential Logic II, Labs, Verilog
1:33:54Sequential Logic II, Labs, Verilog
1:23:51Digital Design and Computer Architecture - L5: HDL, Verilog II, Timing & Verification
1:48:14Digital Design and Computer Architecture - L6: Timing & Verification II
1:49:42Von Neumann Model & Instruction Set Architectures
1:50:32Instruction Set Architectures II
1:47:52ISA and Microarchitecture
1:47:54Assembly Programming
39:59Microarchitecture Fundamentals and Design II
1:47:35Multi-Cycle and Pipelined Processor Design
1:48:05Pipelined Processor Design II
1:48:10Precise Exceptions
1:32:02Out-of-Order Execution
1:36:14Dataflow, Superscalar Execution & Branch Prediction
1:51:29Load-Store Handling in Out-of-Order Execution
24:03Advanced Branch Prediction
1:50:47VLIW and Systolic Array Architectures
1:49:39SIMD Architectures
1:51:16Digital Design and Computer Architecture - L5: HDL, Verilog II, Timing & Verification
This lecture segment from Professor Onur Mutlu's ETH Zürich course delves into advanced aspects of Hardware Description Languages, specifically Verilog for digital circuit description. It examines critical considerations for timing analysis and formal verification methods within complex digital system design.
Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (https://safari.ethz.ch/ddca/spring2025/)
Lecture 5a: Hardware Description Languages and Verilog II
Lecture 5b: Timing and Verification
Sequential Logic II, Labs, Verilog
Next · Lecture 7Digital Design and Computer Architecture - L6: Timing & Verification II