Digital Design and Computer Architecture - L1: Intro: Fundamentals, Transistors, Gates
1:44:24Digital Design and Computer Architecture - L2: Combinational Logic
1:48:06Digital Design and Computer Architecture - L3: Sequential Logic
1:47:35Digital Design and Computer Architecture - L4: Sequential Logic II, Labs, Verilog
1:33:54Sequential Logic II, Labs, Verilog
1:23:51Digital Design and Computer Architecture - L5: HDL, Verilog II, Timing & Verification
1:48:14Digital Design and Computer Architecture - L6: Timing & Verification II
1:49:42Von Neumann Model & Instruction Set Architectures
1:50:32Instruction Set Architectures II
1:47:52ISA and Microarchitecture
1:47:54Assembly Programming
39:59Microarchitecture Fundamentals and Design II
1:47:35Multi-Cycle and Pipelined Processor Design
1:48:05Pipelined Processor Design II
1:48:10Precise Exceptions
1:32:02Out-of-Order Execution
1:36:14Dataflow, Superscalar Execution & Branch Prediction
1:51:29Load-Store Handling in Out-of-Order Execution
24:03Advanced Branch Prediction
1:50:47VLIW and Systolic Array Architectures
1:49:39SIMD Architectures
1:51:16Load-Store Handling in Out-of-Order Execution
This specific session addresses the complex mechanisms of load and store instruction handling within out-of-order execution pipelines. It discusses memory disambiguation and ordering rules to ensure correct program behavior.
Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (
Dataflow, Superscalar Execution & Branch Prediction
Next · Lecture 19Advanced Branch Prediction