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Advanced Branch Prediction
Discover how microprocessors guess the future using two-level history, neural perceptrons, and massive hybrid predictors to maintain peak pipeline performance.
Lecture guide · Written by AI from the lecture. For the lecture’s own words, open the Transcript tab.
Covers advanced hardware branch prediction techniques designed to keep high-performance processor pipelines full and efficient. It explores static compilation methods, dynamic history-based predictors including last-time and saturating counter approaches, two-level global and local history mechanisms, hybrid selectors, and machine learning models like perceptrons and TAGE predictors.
This lecture assumes
- Hashingtaught in Cybersecurity at 46:14
- Perceptrontaught in Introduction to Deep Learning at 14:10
- Neural Networkstaught in Artificial Intelligence at 43:38
Key Takeaways
- Static branch predictors rely on compile-time profiles, heuristics, or programmer-provided pragmas, but cannot adapt to dynamic runtime behavioral changes.
- Two-bit saturating counters add hysteresis to last-time predictors, preventing single atypical outcomes from flipping prediction states.
- Two-level global branch predictors use a Global History Register (GHR) to index into pattern history tables, capturing correlations across different branches.
- GShare predictors improve global prediction by hashing the branch PC with the GHR using an XOR gate, better distributing table entries.
Concepts Explained31
Branch Prediction—Predicting the direction and target of branches so that we can keep the pipeline full without stalling the fetch engine.
Branch Target Buffer (BTB)—A cache of target addresses indexed with the program counter of the instruction you fetch to provide target addresses for predicted branches.
Static Branch Prediction—Branch prediction techniques determined at compile time that do not require complex runtime hardware.
Profile-Based Branch Prediction—A static prediction method where the compiler runs a profile to determine likely branch directions and encodes them as hint bits.
Examples, Proofs & Derivations
Works & Sources Cited23
Paper
The Microarchitecture of Superscalar Processors—Smith and Sohi, Proceedings of the IEEE, 1995
Book
Digital Design and Computer Architecture—H&H Chapters 7.8 and 7.9
Paper
Combining Branch Predictors—McFarling, DEC WRL Technical Report, 1993
Paper
The Alpha 21264 Microprocessor—Kessler, IEEE Micro 1999
Paper
Branch prediction for free—Ball and Larus, PLDI 1993, cited for program-based static branch prediction heuristics.